Placement Algorithm for FPGA Circuits
نویسندگان
چکیده
Field-Programmable Gate Arrays (FPGAs) are flexible and reusable circuits that can be easily reconfigured by the designer. One of the steps involved in the logic design with FPGA circuits is placement. In this step, the logic functions are assigned to specific cells of the circuit. In this paper we present a placement algorithm for FPGA circuits. In traditional min-cut based placement algorithms, the only metric in the cost function is the cut size. The proposed algorithm not only reduces the cut size and balances the size of the two portions, but also evenly distributes the connections among them. We also propose another sequence of slicing lines which reduces the maximum cut size and the total wirelength of the circuit.
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